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INTEGRATED CIRCUITS
DATA SHEET
SZF2002 Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Product specification File under Integrated Circuits, IC20 1998 Aug 26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 9 9.1 9.2 9.3 9.4 9.5 10 11 11.1 11.2 12 12.1 12.2 12.3 12.4 12.5 13 13.1 13.2 14 14.1 14.2 15 15.1 15.2 15.3 15.4 15.5 FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION General CPU timing MEMORY ORGANIZATION Program memory Data memory Special Function Registers (SFRs) Addressing Paging logic PROGRAM STATUS WORD (PSW) I/O FACILITIES Ports Port configuration TIMER/EVENT COUNTERS Timer 0 and Timer 1 Timer 2 Timer/Counter 2 Control Register (T2CON) Timer/Counter 2 Mode Register (T2MOD) Watchdog Timer (T3) PULSE WIDTH MODULATED OUTPUT Prescaler Frequency Control Register (PWMP) Pulse Width Register (PWM) ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Control Register (ADCON) ADC Result Register (ADCH) REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Status of external pins Power Control Register (PCON) 17.1 17.2 17.3 18 18.1 18.2 18.3 19 20 20.1 20.2 21 22 22.1 22.2 22.3 22.4 22.5 23 24 25 26 27 28 29 29.1 29.2 29.3 29.4 30 31 32 16 16.1 16.2 16.3 16.4 17 I2C-BUS SERIAL I/O
SZF2002
Serial Control Register (S1CON) Serial Status Register (S1STA) Data Shift Register (S1DAT) Address Register (S1ADR) STANDARD SERIAL INTERFACE SIO0: UART Multiprocessor communications Serial Port Control and Status Register (S0CON) Baud rates INTERRUPT SYSTEM External interrupts INT2 to INT8 Interrupt priority Interrupt related registers CLOCK CIRCUITRY RESET External reset using the RST pin Power-on-reset SPECIAL FUNCTION REGISTERS OVERVIEW DEBUGGING SUPPORT Recommended equipment Connecting the pod Powering the pod Bank switching support Software recommendations INSTRUCTION SET LIMITING VALUES DC CHARACTERISTICS ADC CHARACTERISTICS AC CHARACTERISTICS PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 Aug 26
2
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
1 FEATURES
SZF2002
* Fully static 80C51 Central Processing Unit (CPU) * 8-bit CPU, ROM, RAM and I/O in a 80 lead LQFP package * 6-kbytes ROM program memory, expandable externally to 256 kbytes * 6144 + 256 bytes low power RAM data memory, expandable externally to 32 kbytes * Internal AUX RAM can be used for program execution (only in combination with internal ROM) * Three 8-bit ports; 24 I/O lines * Three 16-bit timer/event counters * Flash Memory Interface optimized, with power saving and programming options * Internal demultiplexing and latching of address/data bus to reduce system component count * Interfaces to up to 256-kbyte Flash Memory (banked) * Fifteen source, fifteen vector nested interrupt structure with two priority levels * Full duplex serial port (UART) * I2C-bus interface for serial transfer on two lines * Analog-to-Digital Converter (ADC) with Power-down mode; 6 input channels and 8-bit ADC * Pulse Width Modulated (PWM) output (8-bit resolution) * Watchdog Timer * Enhanced architecture with: - Non-page oriented instructions - Direct addressing - Four 8-byte RAM register banks - Stack depth limited only by available internal RAM (maximum 256 bytes) - Multiply, divide, subtract and compare instructions * Modes of reduced activity: Power-down and Idle modes 4 ORDERING INFORMATION TYPE NUMBER SZF2002HL PACKAGE NAME LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm VERSION SOT315-1 3 APPLICATIONS * Wake-up via external interrupts at INT0 to INT8 * Frequency range: up to 16 MHz (only limited by external memory and ADC performance) * Supply voltage: 3.0 V * Very low power consumption: operational 0.65 mW/MHz; Idle 0.25 mW/MHz at 3.0 V * Operating temperature: -40 to +85 C. 2 GENERAL DESCRIPTION
The SZF2002 low power system controller is manufactured in an advanced 0.5 m CMOS technology. The instruction set of the SZF2002 is based on that of the 80C51 and consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte. The device has low power consumption and two software selectable modes for power reduction: Idle and Power-down. This data sheet details the specific properties of the SZF2002; for details of the 80C51 core and peripheral functions such as timers, UART and I/O, see "Data Handbook IC20". For the I2C-bus refer to "The I2C-bus and how to use it", ordering number 9398 393 40011.
The SZF2002 is an 8-bit general purpose microcontroller especially suited for wireless telephone and battery powered applications. The SZF2002 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities.
1998 Aug 26
3
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
5 BLOCK DIAGRAM
SZF2002
INT0 T0 T1
INT2 to INT8 VDD 3 VSS 3 PWM VDDA VSSA
ADC0 to ADC5
INT1
XCLK RST CE OE WE 80C51 core excluding ROM/RAM TWO 16-BIT TIMER/ EVENT COUNTERS (T0, T1) PROGRAM MEMORY CPU 6-KBYTE ROM DATA MEMORY 6144 + 256 bytes RAM PWM ADC
RAMCE
EA DEBUG D0 to D7
SZF2002
A0 to A17
PARALLEL I/O PORTS AND EXT. BUS
SERIAL UART PORT
8-BIT I/O PORTS
16-BIT TIMER/ EVENT COUNTER
I2C-BUS INTERFACE
WATCHDOG TIMER (T3)
MGM180
P1
P3
TXD RXD
P4
T2
T2EX
SDA
SCL
(1) Address lines A0 to A5 have alternative functions during Debug; see Section 7.2.
Fig.1 Block diagram.
1998 Aug 26
4
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
6 FUNCTIONAL DIAGRAM
SZF2002
handbook, full pagewidth
XCLK WE OE CE PWM
0
T2 T2EX
PORT 1
SCL SDA 0 RXD TXD INT0 INT1 T0 T1
INT2 INT3 INT4 INT5 INT6 INT7 INT8
VSSA VDDA VSS 3 PORT 3
VDD 3 0 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5
SZF2002
data bus
RAMCE
0
0
RD WR ALE PSEN RST TRUE_A15
PORT 4
address bus RST
EA DEBUG
MGM181
Fig.2 Functional diagram.
1998 Aug 26
5
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
7 7.1 PINNING INFORMATION Pinning
SZF2002
70 VDD
71 VSS
79 A15
78 A16
76 A17
75 A14
74 A13
69 A11
80 n.c.
n.c. A12 A7 A6 A5 A4 PWM RST XCLK
1 2 3 4 5 6 7 8 9
61 n.c. 60 n.c. 59 D3 58 D2 57 D1 56 D0 55 A0 54 A1 53 A2 52 A3 51 VSS 50 VDD 49 P4.0/RAMCE 48 P4.1 47 P4.2 46 P4.3 45 P4.4 44 P4.5 43 P4.6 42 P4.7 41 n.c. n.c. 40
77 WE
68 OE
66 CE
65 D7
64 D6
63 D5 EA 38
VDD 10
SZF2002
VSS 11 P3.7 12 P3.6 13 P3.5/T1 14 P3.4/T0 15 P3.3/INT1 16 P3.2/INT0 17 P3.1/TXD 18 P3.0/RXD 19 n.c. 20 n.c. 21 P1.7/SDA 22 P1.6/INT8/SCL 23 P1.5/INT7 24 P1.4/INT6 25 P1.3/INT5 26 P1.2/INT4 27 P1.1/INT3/T2EX 28 P1.0/INT2/T2 29 VDDA 30 VSSA 31 ADC5 32 ADC4 33 ADC3 34 ADC2 35 ADC1 36 ADC0 37 DEBUG 39
62 D4
73 A8
72 A9
handbook, full pagewidth
67 A10
MGM182
Fig.3 Pin configuration.
1998 Aug 26
6
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
7.2 Pin description LQFP80 package PIN DESCRIPTION
SZF2002
Table 1
SYMBOL
Program memory interface; note 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 CE OE WE 55 54 53 52 6 5 4 3 73 72 67 69 2 74 75 79 78 76 56 57 58 59 62 63 64 65 66 68 77 Chip Enable. Enable strobe to external program memory. Output Enable. Output read strobe to external memory. Write Enable. Write strobe to external memory. Data bus. During Debug these line are P0.0 to P0.7. Address lines A15 to A17. Page selection; during Debug these lines are the page register. Each bank is 32 kbytes. A0/RD. Address line 0, used as RD during Debug. A1/WR. Address line 1, used as WR during Debug. A2/ALE. Address line 2, used as ALE during Debug. A3/PSEN. Address line 3, used as PSEN during Debug. A4/RST. Address line 4, used as RST during Debug. A5/TRUE_A15. Address line 5, used as A15 = P2.7 during Debug. A6. Address line 6 (not needed during Debug, see D6). A7. Address line 7 (not needed during Debug, see D7). Address lines A8 to A14. During Debug these lines are used as P2.0 to P2.6.
1998 Aug 26
7
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SYMBOL I/O Ports P1.0/INT2/T2 P1.1/INT3/T2EX P1.2/INT4 P1.3/INT5 P1.4/INT6 P1.5/INT7 P1.6/INT8/SCL P1.7/SDA P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6 P3.7 P4.0/RAMCE P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 ADC interface ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 37 36 35 34 33 32 Input channels to the ADC. 29 28 27 26 25 24 23 22 19 18 17 16 15 14 13 12 49 48 47 46 45 44 43 42 PIN DESCRIPTION
SZF2002
Port 1 (P1.0 to P1.7). 8-bit bidirectional I/O port with internal pull-ups; INT2 to INT8: external interrupt inputs; T2: Timer T2 I/O; T2EX: Timer 2 external input; SCL: I2C-bus interface clock; SDA: I2C-bus interface data. Port 1 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups, and in that state can be used as inputs (note P1.6 and P1.7 are open-drain only). As inputs, Port 1 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.
Port 3 (P3.0 to P3.7). 8-bit bidirectional I/O port with internal pull-ups; RXD: serial port receiver data input (asynchronous); TXD: serial port transmitter data output (asynchronous); INT0: external interrupt 0; INT1: external interrupt 1; T0: Timer 0 external input; T1: Timer 1 external input. Port 3 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.
Port 4 (P4.0 to P4.7). 8-bit bidirectional I/O port; RAMCE chip enable for external RAM. Port 4 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 4 pins that are externally pulled LOW will source current (IIL, see Chapter 25) due to the internal pull-ups.
1998 Aug 26
8
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SYMBOL General PWM RST XCLK EA 7 8 9 38 Pulse Width Modulation output. PIN DESCRIPTION
SZF2002
Reset. A HIGH level on this pin for at least 12 clock cycles resets the device. Clock input. External Access. When EA is HIGH the CPU executes out of internal program memory (unless the program counter exceeds 7FFFH). A LOW EA forces the CPU to execute out of external memory regardless of the value of the Program Counter. This signal is latched at the falling edge of reset (RST pin). The EA pin has an internal pull-down. When it is not connected the CPU executes from external memory. DEBUG enable. If HIGH, forces standard 80C51 timing signals output at address and databus. In this mode the databus is multiplexed with the lower 8 bits of the address bus, and the A0 to A3 lines are used for the RD, WR, ALE and PSEN signals. This allows a standard 80C51 in-circuit emulator to be connected. For normal operation connect DEBUG to VSS. Power supply digital core and digital I/O pads. Ground: circuit ground potential. Analog power. Analog ground. Not connected.
DEBUG
39
Power VDD VSS VDDA VSSA n.c. 10, 50, 70 11, 51, 71 30 31 1, 20, 21, 40, 41, 60, 61, 80
Note 1. The pin layout has been optimized for easy connection of 256 kbytes Flash ROM (e.g. ATMEL AT29LV010A, SGS-Thomson M28V201, or AMD Am29F010).
1998 Aug 26
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
8 FUNCTIONAL DESCRIPTION
SZF2002
The SZF2002 contains a 6-kbyte program memory; a static 6144 + 256 byte data memory (RAM); 24 I/O lines; three 16-bit timer/event counters; a fifteen-source two priority-level, nested interrupt structure, a 6-channel 8-bit ADC, a Watchdog Timer and a Pulse Width Modulation output. Two serial interfaces are provided on-chip: * A standard UART serial interface * A standard I2C-bus serial interface with a transfer speed of up to 400 kbits/s (depending on clock frequency). The I2C-bus serial interface has byte oriented master and slave functions allowing communication with the whole family of I2C-bus compatible devices. The device has two software selectable modes of reduced activity for power reduction: * Idle mode: freezes the CPU while allowing the derivative functions (timers, serial I/O, RAM, ADC and PWM) and interrupt system to continue functioning * Power-down mode: saves the RAM contents but stops the clock causing all other chip functions to be inoperative. 8.2 CPU timing
Detailed descriptions of each function are described in: Chapter 9 "Memory organization" Chapter 10 "Program Status Word (PSW)" Chapter 11 "I/O facilities" Chapter 12 "Timer/event counters" Chapter 13 "Pulse Width Modulated output" Chapter 14 "Analog-to-digital converter (ADC)" Chapter 15 "Reduced power modes" Chapter 16 "I2C-bus serial I/O" Chapter 17 "Standard serial interface SIO0: UART" Chapter 18 "Interrupt system" Chapter 19 "Clock circuitry" Chapter 20 "Reset" Chapter 21 "Special Function Registers overview" Chapter 22 "Debugging support". 8.1 General
The SZF2002 is a stand-alone high-performance CMOS microcontroller designed for use in real-time applications such as wireless telephone and mobile communications, instrumentation, industrial control, intelligent computer peripherals and consumer products. The device provides hardware features, architectural enhancements and new instructions to function as a controller for applications requiring up to 256 kbytes of program memory and/or up to 6144 + 256 bytes of on-chip data memory.
A machine cycle consists of a sequence of 6 states. Each state lasts one clock period, thus a machine cycle takes 6 clock periods or 1 s if the clock frequency (fclk) is 6 MHz.
1998 Aug 26
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
9 MEMORY ORGANIZATION
SZF2002
The Special Function Register locations 128 to 255 are only directly addressed. Auxiliary RAM is accessible via MOVX instructions to the lower 32-kbyte address space. MOVX @R0/R1 instructions use SFR P2 as page selector. The upper 32-kbyte address space is redirected to the program memory, to accommodate flash programming. 9.3 Special Function Registers (SFRs)
The SZF2002 has 6 kbytes of program memory plus 6 kbytes + 256 bytes of data memory on chip. The device has separate address spaces for program and data memory (see Fig.4). The SZF2002 can directly address up to 256 kbytes of external data memory. The CPU generates the read strobe (OE), the write strobe (WE) and chip select (CE) for external program memory (Flash), and read strobe (OE) and write strobe (WE) and chip select (RAMCE) for external data memory. 9.1 Program memory
The SZF2002 contains 6 kbytes of internal ROM and 6144 + 256 bytes of RAM. The lower 6 kbytes of program memory can be implemented in either on-chip ROM or external program memory. The 6 kbytes of program memory is implemented as mask programmable ROM. There are two modes for the program memory, depending on the state of the EA pin (latched during reset) and on the address range: 1. EA = 0. All program fetches are directed to the external program memory. After reset the CPU begins execution at location 8000H. 2. EA = 1. After reset the CPU begins execution at location 0000H. Fetches from addresses 2000H to 37FFH are redirected to the Auxiliary RAM. The processor can fill this RAM with normal write operations to the data memory (MOVX to addresses 0000H to 17FFH). Program memory fetches from addresses 0000H to 17FFH are directed to the internal ROM. Program Counter values greater than 7FFFH are automatically addressed to external memory regardless of the state of the EA pin. 9.2 Data memory
The upper 128 bytes are the address locations of the SFRs. Figures 6 and 7 show the Special Function Registers space. The SFRs include the port latches, timers, peripheral control, serial I/O registers, etc. These registers are accessed by direct addressing. There are 128 directly addressed locations in the SFR address space. Bit addressed SFRs are those that end in 000B. 9.4 Addressing
The SZF2002 has five methods for addressing source operands: * Register * Direct * Indirect * Immediate * Base-Register plus Index-Register-Indirect. The first three methods can be used for addressing destination operands. Most instructions have a `destination/source' field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addressing is as follows: * Registers in one of the four register banks through Direct or Indirect (see Fig.5) * Lower 128 bytes of internal RAM through Direct or register Indirect; upper 128 bytes of internal RAM through Indirect * Special Function Registers through Direct * Program memory look-up tables through Base-Register plus Index-Register-Indirect * Extended data memory access through register Indirect.
The SZF2002 contains 6144 + 256 bytes of RAM and a number of Special Function Registers (SFRs). All these data spaces are addressed differently. Figure 4 shows the internal data memory space divided into the lower 128 bytes, the upper 128 bytes, Auxiliary RAM, and the SFRs space. Internal RAM locations 0 to 127 are directly and indirectly addressed. Internal RAM locations 128 to 255 are only indirectly addressed.
1998 Aug 26
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
FFFFH
FFFFH
EXTERNAL FLASH ROM (BANKED)
EXTERNAL FLASH ROM (BANKED)
8000H
7FFFH 37FFH EXTERNAL ROM BANK 0
2000H 17FFH
0000H EA = 0
0000H
,,, ,,, ,,, ,,,
INTERNAL AUX RAM 6-KBYTE INTERNAL ROM EA = 1(4)
8000H
7FFFH overlapped space
EXTERNAL RAM 1800H 17FFH INTERNAL AUX RAM 0000H (MOVX) DATA MEMORY FFH 80H 00H
(2)
(1)
INTERNAL RAM
SPECIAL FUNCTION (3) REGISTERS
PROGRAM MEMORY
INTERNAL MEMORY
MGM183
(1) (2) (3) (4)
Accessible via indirect addressing only. Accessible via direct and indirect addressing. Accessible via direct addressing. Gaps in the address map are undefined, and should not be used.
Fig.4 Memory map.
Table 2
Memory spaces; note 1 MEMORY SPACE ADDRESS MODE direct and indirect indirect direct MOVX MOVX program execution program execution MOVX USED SIGNAL - - - - RAMCE, OE and WE CE, OE - CE, OE and WE
Internal RAM 00H to 7FH Internal RAM 80H to FFH SFRs 80H to FFH Internal AUX RAM (on-chip) 0000H to 17FFH External RAM (off-chip) 1800H to 7FFFH External ROM (off-chip) 0000H to FFFFH; note 2 Internal AUX RAM (on-chip) 2000H to 37FFH External Flash ROM write (off-chip) 8000H to FFFFH; note 2 Notes
1. Execution from internal memory is only possible when EA = 1 during reset. 2. Page select is used to access all 8 banks in the 256-kbyte address space.
1998 Aug 26
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
9.5 Paging logic
SZF2002
The SZF2002 contains paging logic to handle the extended address range. Table 3 Paging of external memory; notes 1 and 2 BANK SFR [2 : 0] XXX 000 001 010 011 100 101 110 111 A<17-15> PINS 000 000 001 010 011 100 101 110 111 BANK 0 0 1 2 3 4 5 6 7 REMARK lower 32 kbytes always bank 0 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7
TRUE_A15 (INTERNAL) 0 1 1 1 1 1 1 1 1 Notes
1. During Debug A<17-15> are used to output the bank register. The TRUE_ A15 line is output at the A5 pin. 2. During Debug ROM and RAM access is done via PSEN, WR and RD.
handbook, halfpage
7FH
30H 2FH
R7 R0 R7 R0 R7 R0 R7 R0
20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7)
MGD675
Fig.5 The lower 128 bytes of internal RAM.
1998 Aug 26
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS (HEX)
T3 PWMP
FFH FEH FDH
PWM IP1 WDTKEY B F7 F6 F5 F4 F3 F2 F1 F0 FF FE FD FC FB FA F9 F8
FCH F8H F7H F0H EFH EEH EDH ECH EBH EAH
IX1 IEN1 ACC S1ADR S1DAT S1STA S1CON PSW DF DE DD DC DB DA D7 D6 D5 D4 D3 D2 D9 D1 D8 D0 EF EE ED EC E7 E6 E5 E4 EB EA E3 E2 E9 E1 E8 E0
E9H E8H E0H DBH DAH D9H D8H D0H CFH CEH SFRs containing directly addressable bits
TH2 TL2 RCAP2H RCAP2L T2MOD T2CON ADCH ADCON P4 IRQ1 C7 C6 C5 C4 C3 C2 C1 C0 CF CE CD CC CB CA C9 C8
CDH CCH CBH CAH C9H C8H C5H C4H C1H C0H
MGM184
Fig.6 Special Function Register memory map.
1998 Aug 26
14
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
REGISTER MNEMONIC
BIT ADDRESS
DIRECT BYTE ADDRESS
IP0 P3 B7
BE BD BC B6 B5 B4
BB BA B3 B2
B9 B1
B8 B0
B8H B0H AFH AEH ADH ACH ABH AAH A9H
IEN0 (used as address bus) P2
AF AE AD AC A7 A6 A5 A4
AB AA A3 A2
A9 A1
A8 A0
A8H A0H 9AH SFRs containing directly addressable bits
S0BUF S0CON ROMBANK P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP (used as P0 address bus) 87 86 85 84 83 82 81 80 8F 8E 8D 8C 8B 8A 89 88 97 96 95 94 93 92 91 90 9F 9E 9D 9C 9B 9A 99 98
99H 98H 91H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H
MGM185
Fig.7 Special Function Register memory map (continued from Fig.6).
1998 Aug 26
15
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
10 PROGRAM STATUS WORD (PSW) The Program Status Word contains several status bits that reflect the current state of the CPU. The PSW, shown in Table 4, resides in the SFR memory space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags. The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the Accumulator for a number of boolean operations. Bits RS0 and RS1 are used to select one of the four register banks; see Table 5. A number of instructions refer Table 4 7 CY Table 5 BIT 7 6 5 4 3 2 1 0 Program Status Word (SFR address D0H) 6 AC Description of PSW bits SYMBOL CY AC F0 RS1 RS0 OV USR P DESCRIPTION 5 F0 4 RS1 3 RS0 2 OV 1 USR
SZF2002
to these RAM locations as R0 through to R7. The selection of which of the four register banks is being referred to is made on the basis of the state of RS0 and RS1 at execution time. The Parity bit reflects the number of 1s in the Accumulator: P = 1, if the Accumulator contains an odd number of 1s, and P = 0, if the Accumulator contains an even number of 1s. Thus, the number of 1s in the Accumulator plus P is always even. The bits F0 and USR are uncommitted and may be used as general purpose status flags.
0 P
Carry flag. The Carry flag receives carry out from bit 7 of ALU operands. Auxiliary Carry flag. The Auxiliary Carry flag receives carry out from bit 3 of addition operands. General purpose status flag. Register Bank Select 1. This bit selects Register Bank 1. Register Bank Select 0. This bit selects Register Bank 0. Overflow flag. This flag is set by arithmetic operations. USR. This is a user-definable flag. Parity. If the Accumulator contains an odd number of 1s this bit is set to a logic 1 by hardware. Otherwise, the state of this bit is a logic 0.
1998 Aug 26
16
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
11 I/O FACILITIES 11.1 Ports
SZF2002
Port 4 Provides chip select for external data memory: RAMCE. To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1. Each port consists of a latch (SFRs P0 to P4), an output driver and input buffer. Ports 1, 3 and 4 have internal pull-ups (except P1.6 and P1.7). Figure 8 shows that the strong transistor `p1' is turned on for only 2 clock periods after a LOW-to-HIGH transition in the port latch. When on, it turns on `p3' (a weak pull-up) through the inverter. This inverter and `p3' form a latch which holds the logic 1. In Port 0 the pull-up `p1' is only on when emitting logic 1s for external memory access. 11.2 Port configuration
The SZF2002 has 24 I/O lines: ports P1, P3 and P4 of which ports P1 and P3 are bit addressed (P0 and P2 are always used as address/data bus). Ports 0 to 4 have the following alternative functions: Port 0 Used internally. Port 1 Used for a number of special functions: * Provides the inputs for the external interrupts: INT2 to INT8 * The I2C-bus interface: SCL and SDA * Counter inputs: T2 and T2EX. Port 2 Used internally. Port 3 Pins can be configured individually to provide: * External interrupt request inputs: INT1 and INT0 * Counter input: T1 and T0 * UART input and output: RXD and TXD.
The port pins (except for P1.6 and P1.7) are configured as shown in Fig.8. This is a quasi-bidirectional I/O with pull-up. The strong booster pull-up `p1' is turned on for one clock period after a LOW-to-HIGH transition in the port latch. All port pins will be set to HIGH during reset.
handbook, full pagewidth
strong pull-up 2 clock periods p1
VDD
p2 p3 I/O pin
Q from port latch
n
input data read port pin INPUT BUFFER
MBK456
Fig.8 Port configuration.
1998 Aug 26
17
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
12 TIMER/EVENT COUNTERS The SZF2002 contains three 16-bit timer/event counter registers; Timer 0, Timer 1 and Timer 2 which can perform the following functions: * Measure time intervals and pulse duration * Count events * Generate interrupt requests. In the `Timer' operating mode the register increments every machine cycle. Since a machine cycle consists of 6 clock periods, the count rate is 16fclk. In the `Counter' operating mode, the register increments in response to a HIGH-to-LOW transition. Since it takes 2 machine cycles (12 clock periods) to recognize a HIGH-to-LOW transition, the maximum count rate is 1 f . To ensure a given level is sampled, it should be 12 clk held for at least one complete machine cycle. 12.1 Timer 0 and Timer 1
SZF2002
* If EXEN2 = 1, Timer 2 operates as already described but with the additional feature that a HIGH-to-LOW transition at external input T2EX causes the current value in TL2 and TH2 to be captured into registers RCAP2L and RCAP2H respectively. In addition, the transition at T2EX causes the EXF2 bit in T2CON to be set; this may also be used to generate an interrupt. 12.2.2 AUTO-RELOAD MODE
Figure 10 shows the Auto-reload mode. * Counting up (DCEN = 0) In the Auto-reload mode and counting up, registers RCAP2L/RCAP2H are used to hold a reload value for TL2 /TH2 when Timer 2 rolls over. By setting/clearing bit EXEN2 in T2CON the external trigger input pin T2EX can be enabled/disabled. If EXEN2 = 0, then Timer 2 is a 16-bit timer/counter which upon overflow sets TF2, and reloads TL2/TH2 with the reload value held in RCAP2L/RCP2H. If EXEN2 = 1, then Timer 2 performs as above, but with the added feature that a HIGH-to-LOW transition at pin T2EX causes the current Timer 2 value (TL2/TH2 data) to be reloaded with the value held in RCAP2L/RAP2H, and bit EXF2 in T2CON to be set. Timer 2 interrupt will be set if EXF2 is set or TF2 is set. * Counting up (DCEN = 1 and T2EX = 1). In this mode Timer 2 will count up. When the timer overflows (FFFFH state), TF2 bit will be set. This will reload TL2 and TH2 with the contents of T2CAPL and T2CAPH, respectively. Also bit EXF2 will be toggled. Bit EXF2 can be used as the 17th bit if desired. Timer 2 interrupt will be set only if TF2 is set. * Counting down (DCEN = 1 and T2EX = 0. In this mode Timer 2 will be counting down. Underflow will occur when the contents of TL2/TH2 matches the contents of RCAP2L/RCAP2H. A Timer 2 roll-over from 0000H to FFFFH is not considered as an underflow. Upon underflow, bit TF2 will be set and registers TL2/TH2 will be loaded with FFFFH. In addition, an underflow will cause bit EXF2 to toggle, such that it can be used as the 17th bit if desired. Timer 2 interrupt will be set only if TF2 is set. 12.2.3 BAUD RATE GENERATOR MODE
Timer 0 and Timer 1 can be programmed independently to operate in four modes: Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler. Mode 1 16-bit time-interval or event counter. Mode 2 8-bit time-interval or event counter with automatic reload upon overflow. Mode 3 Timer 0 establishes TL0 and TH0 as two separate counters. 12.2 Timer 2
Timer 2 is a 16-bit timer/up-down counter that can operate (like Timer 0 and 1) either as a timer or as an event counter. These functions are selected by the state of the C/T2 bit in the T2CON register; see Section 12.3. Three operating modes are available: Capture, Auto-reload and Baud Rate Generator, which also are selected via the T2CON register. 12.2.1 CAPTURE MODE
Figure 9 shows the Capture mode. Two options in this mode may be selected by the EXEN2 bit in T2CON: * If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter that sets the Timer 2 overflow bit (TF2) on overflow, this can be used to generate an interrupt.
The Baud Rate Generator mode is selected when RCLK0 = 1 or TCLK0 = 1 or RCLK1 = 1 or TCLK1 = 1. It will be described in conjunction with the serial port (UART); see Section 17.3.2.
1998 Aug 26
18
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
fclk
6
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 capture Timer 2 interrupt RCAP2L RCAP2H EXF2
MGM136
transition detector T2EX PIN control EXEN2
Fig.9 Timer 2 in Capture mode.
handbook, full pagewidth
fclk
6
C/T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
T2 PIN
C/T2 = 1
control TR2 reload Timer 2 interrupt RCAP2L RCAP2H
transition detector T2EX PIN control EXEN2
EXF2
MGM137
Fig.10 Timer 2 in Auto-reload mode.
1998 Aug 26
19
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
12.3 Timer/Counter 2 Control Register (T2CON) Timer/Counter 2 Control Register (SFR address C8H) 6 EXF2 5 RCLK0 4 TCLK0 3 EXEN2 2 TR2 1 C/T2
SZF2002
Table 6 7 TF2 Table 7 BIT 7
0 CP/RL2
Description of T2CON bits SYMBOL TF2 DESCRIPTION Timer 2 overflow flag. Set by a Timer 2 underflow or overflow and must be cleared by software. TF2 will not be set when in either the Baud Rate generation mode or Clock out mode. Timer 2 external flag. Set when either a capture or reload is caused by a negative transition on T2EX and when EXEN2 = 1. In Auto-reload mode it is toggled on an underflow or overflow. Cleared by software. Receive clock 0 flag. When set, causes the UART to use Timer 2 overflow pulses. RCLK0 = 0, causes Timer 1 overflow pulses to be used. Transmit clock 0 flag. When set, causes the UART to use Timer 2 overflow pulses. TCLK0 = 0, causes Timer 1 overflow pulses to be used. Timer 2 external enable flag. When set, allows a capture or reload to occur, together with an interrupt, as a result of a negative transition on input T2EX (if in Capture mode or Auto-reload mode with DCEN reset). If in Auto-reload mode and DCEN is set, this bit has no influence. In the other modes EXF2 is set and an interrupt is generated on a HIGH-to-LOW transition on T2EX pin. In all modes EXEN2 = 0, causes Timer 2 to ignore events at T2EX. Timer 2 start/stop control. When TR2 = 1, Timer 2 is started. Timer or counter select for Timer 2. C/T2 = 0, selects the internal timer with a clock frequency of 16fclk. C/T2 = 1, selects the external event counter; negative edge triggered. Capture/Reload flag. Selection of Capture or Auto-reload mode.
6
EXF2
5 4 3
RCLK0 TCLK0 EXEN2
2 1
TR2 C/T2
0
CP/RL2
1998 Aug 26
20
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
12.4 Timer/Counter 2 Mode Register (T2MOD) Timer/Counter 2 Mode Register (SFR address C9H) 6 - 5 RCLK1 4 TCLK1 3 - 2 T2RD 1 T2OE
SZF2002
Table 8 7 -
0 DCEN
Description of T2MOD bits BIT 7 6 5 4 3 2 1 0 SYMBOL - - RCLK1 TCLK1 - T2RD T2OE DCEN Receive Clock 1 flag. Reserved for future UART2. When set, causes the UART to use Timer 2 overflow pulses. RCLK1 = 0, causes Timer 1 overflow pulses to be used. Transmit Clock 1 flag. Reserved for future UART2. When set, causes the UART to use Timer 2 overflow pulses. TCLK1 = 0, causes Timer 1 overflow pulses to be used. This bit is reserved. Timer 2 Read flag. This bit is set by hardware if following a TL2 read and before a TH2 read, TH2 is incremented. It is reset on the trailing edge of the next TL2 read. Timer 2 Output Enable. When set, output is activated to output a clock at the T2 pin (Clock output mode). Down Count Enable. When set, this allows Timer 2 to be configured as an up/down counter. These 2 bits are reserved. DESCRIPTION
Table 9
Timer 2 operating modes; note 1 CP/RL2 0 1 X T2OE 0 0 X C/T2 X X X MODE 16-bit Auto-reload 16-bit Capture Baud Rate Generator
RCLK0 + TCLK0 + RCLK1 + TCLK1 0 0 1 Note 1. X = don't care
1998 Aug 26
21
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
12.5 Watchdog Timer (T3)
SZF2002
If the processor suffers a hardware/software malfunction, the software will fail to reload the timer.This failure will produce a reset upon overflow thus preventing the processor running out of control. The Watchdog Timer can only be reloaded if the condition flag WLE (PCON.4) has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared. After reset the Watchdog Timer is off. The Watchdog Timer is started by loading a value into T3. The time interval between the timer reloading and the occurrence of a reset is dependent upon the reloaded value. The time interval is derived from the clock and the value programmed into T3 and may be calculated as shown below: ( 256 - T3 ) T reload = ----------------------------f timer For example, this time period may range from 2 to 500 ms when using a clock frequency fclk = 6 MHz.
In addition to Timer 2 and the standard timers, a Watchdog Timer (consisting of an 11-bit prescaler and an 8-bit timer) is also available. The Watchdog Timer is controlled by the Watchdog Enable Register (WDTKEY). When WDTKEY = 55H, the timer is disabled and the Power-down mode is enabled. Otherwise, the timer is enabled and the Power-down mode is disabled. In the Idle mode the Watchdog Timer and reset circuitry remain active. The Watchdog Timer is shown in Fig.11. The timer frequency is derived from the clock frequency using the formula shown below: f clk f timer = -----------------------------------------( 6 x 2048 ) x T3 When a timer overflow occurs, the microcontroller is reset. To prevent a system reset the timer must be reloaded in time by the application software.
handbook, full pagewidth
INTERNAL BUS
fclk/6
PRESCALER 11-BIT
CLEAR
TIMER T3 (8-BIT)
LOAD LOADEN
overflow RST
internal reset
CLEAR
write T3
WLE PCON.4
PD
LOADEN
R RST
PCON.1
SFR WDTKEY INTERNAL BUS
MGM141
Fig.11 Functional diagram of the Watchdog Timer (T3).
1998 Aug 26
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
13 PULSE WIDTH MODULATED OUTPUT One Pulse Width Modulated output channel PWM is provided which outputs pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler (PWMP) that generates the clock for the counter. The 8-bit counter counts modulo 255, i.e. from 0 to 254 inclusive. The value held in the 8-bit counter is compared to the contents of the register PWM. If a new prescaler value is written in register PWMP the 8-bit counter finishes uninterrupted, and the new prescaler value is used in the next count cycle. Provided the contents of this register are greater than the counter value, the PWM output is set HIGH. If the contents of register PWMP are equal to, or less than the counter value, the PWM output is set LOW. The pulse-width-ratio is therefore defined by the contents of register PWM. The pulse-width-ratio will be in the range 0 to 255255 and may be programmed in increments of 1255.
SZF2002
The repetition frequency (fPWM) at the PWM output is given by: f clk f PWM = ---------------------------------------------------------------( 1 + PWMP ) x 255 x 2 For fclk = 12 MHz, the above formula gives a repetition frequency range of 92 Hz to 23.5 kHz. By loading the PWM register with either 00H or FFH, the PWM output can be retained at a constant LOW or HIGH level respectively. When loading FFH into the PWM register, the 8-bit counter will never actually reach this value. The PWM output pin is not shared with any other function.
handbook, full pagewidth
I N T E R N A L B U S PWMP + DIVIDE-BY-2
PWM
8-BIT COMPARATOR
OUTPUT BUFFER
PWM
fclk
8-BIT COUNTER
MGM140
Fig.12 Functional diagram of Pulse Width Modulated output (PWM).
1998 Aug 26
23
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
PWM x 2 x (PWMP + 1) x tclk
PWM 255 x 2 x (PWMP + 1) x tclk
MGM186
Fig.13 PWM signals.
13.1
Prescaler Frequency Control Register (PWMP)
Table 10 Prescaler Frequency Control Register (SFR address FEH) 7 PWMP.7 6 PWMP.6 5 PWMP.5 4 PWMP.4 3 PWMP.3 2 PWMP.2 1 PWMP.1 0 PWMP.0
Table 11 Description of PWMP bits BIT 7 to 0 13.2 SYMBOL PWMP.7 to PWMP.0 DESCRIPTION prescaler division factor = (PWMP) + 1
Pulse Width Register (PWM)
Table 12 Pulse Width Register (SFR address FCH) 7 PWM.7 6 PWM.6 5 PWM.5 4 PWM.4 3 PWM.3 2 PWM.2 1 PWM.1 0 PWM.0
Table 13 Description of PWM bits BIT 7 to 0 SYMBOL PWM.7 to PWM.0 DESCRIPTION ( PWM ) HIGH/LOW ratio of PWM signal = ---------------------------------------------{ 255 - ( PWM ) }
1998 Aug 26
24
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
14 ANALOG-TO-DIGITAL CONVERTER (ADC) The analog input circuitry consists of a 6-input analog multiplexer and an ADC with 8-bit resolution. The analog supply (VDDA) and analog ground (VSSA) are connected via separate input pins. For clock frequencies higher than 8 MHz the clock prescaler is needed (divide-by-2). The functional diagram of the ADC is shown in Fig.14. The ADC is controlled using the ADC Control Register (ADCON). Input channels are selected by the analog multiplexer via the ADCON register bits AADR0 to AADR2. A conversion is started by setting the ADCS bit in the ADCON register. The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register, which will generate an interrupt if this is enabled (EAD). The result is stored in the Special Function Register ADCH (address C5H). To save power the ADC current is switched on only during conversion and is independent of the processor mode (active, Idle or Power-down). If the processor goes into Idle or Power-down mode, the ADC interrupt must be used to wake-up the CPU again.
SZF2002
While ADCS = 1 or ADCI = 1, a new ADC start will be blocked and consequently lost, however an ADC conversion already in progress will finish uninterrupted. An ADC conversion already in progress is aborted when the Power-down mode is entered. The result of a completed conversion (ADCI = 1) remains unaffected when entering the Idle or Power-down mode. When no result of a completed conversion (ADCI = 0) is available, the ADCON and ADCH registers will be reset when entering the Power-down mode. Note that AADRx and CKDIV have to be set explicitly to restore their previous values for the first conversion after Power-down mode. Table 14 Conversion time in clock cycles CONDITION fclk 8 MHz, CKDIV = 0 fclk > 8 MHz, CKDIV = 1 MAX. 288 576 REMARK normal conversion prescaler used
handbook, full pagewidth
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ANALOG INPUT MULTIPLEXER 8-BIT ADC (succesive approximation)
VDDA
VSSA
ADCON
(1)
0
1
2
3
4
5
6
7 Power-down
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
MGM187
(1) For the descriptions of ADCON bits see Table 16.
Fig.14 Functional diagram of analog input.
1998 Aug 26
25
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
14.1 ADC Control Register (ADCON)
SZF2002
Table 15 ADC Control Register (SFR address C4H) 7 - 6 - 5 CKDIV 4 ADCI 3 ADCS 2 AADR2 1 AADR1 0 AADR0
Table 16 Description of ADCON bits BIT 7 6 5 4 SYMBOL - - CKDIV ADCI Prescaler select. When CKDIV = 1, the ADC clock prescaler is used (divide-by-2). Prescaling is necessary with clocks over 8 MHz. ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read. An interrupt is invoked if this is enabled (EAD). This flag must be cleared by software, (it cannot be set by software). ADC start and status flag. When this bit is set an ADC conversion is started. ADCS must be set by software. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion ADCI is set and one clock later the ADCS flag is reset. ADCS cannot be reset by software. Analog input select. These bits are used to select one of the six analog inputs; see Table 17. These 2 bits are reserved. DESCRIPTION
3
ADCS
2 1 0
AADR2 AADR1 AADR0
Table 17 Selection of analog input channel AADR2 0 0 0 0 1 1 1 1 14.2 AADR1 0 0 1 1 0 0 1 1 AADR0 0 1 0 1 0 1 0 1 SELECTED CHANNEL ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 reserved reserved
ADC Result Register (ADCH)
Table 18 ADC Result Register (SFR address C5H) 7 ADC7 6 ADC6 5 ADC5 4 ADC4 3 ADC3 2 ADC2 1 ADC1 0 ADC0
Table 19 Description of ADCH bits BIT 7 to 0 SYMBOL ADC7 to ADC0 8-bit ADC result DESCRIPTION
1998 Aug 26
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
15 REDUCED POWER MODES There are two software selectable modes of reduced activity for further power reduction: Idle and Power-down. 15.1 Idle mode 15.1.2
SZF2002
TERMINATION OF THE IDLE MODE USING AN
EXTERNAL HARDWARE RESET
Idle mode operation permits the interrupt, serial ports, timer blocks, PWM and ADC to continue to function while the clock to the CPU is halted. The following functions remain active during the Idle mode: * Timer 0, Timer 1, Timer 2 and Timer 3 (Watchdog Timer) * UART, I2C-bus interface * Internal interrupt * External interrupt * PWM * ADC. These functions may generate an interrupt or reset; thus ending the Idle mode. The instruction that sets bit IDL (PCON.0) is the last instruction executed in the normal operating mode before the Idle mode is activated. Once in Idle mode, the CPU status is preserved along with the Stack Pointer, Program Counter, Program Status Word, SFRs and Accumulator. The RAM and all other registers maintain their data during Idle mode. The status of the external pins during Idle mode is shown in Table 20. 15.1.1 TERMINATION OF THE IDLE MODE USING AN
ENABLED INTERRUPT
The second way of terminating the Idle mode is with an external hardware reset, or an internal reset caused by an overflow of Timer 3 (Watchdog Timer). Since the clock is still running, the hardware reset is required to be active for two machine cycles (12 clock periods) to complete the reset operation. Reset redefines all SFRs but does not affect the on-chip RAM. 15.2 Power-down mode
The Power-down operation freezes the SZF2002. The Power-down mode can only be activated by setting the PD bit in the PCON register. The instruction that sets PD (PCON.1) is the last executed prior to going into the Power-down mode. Once in the Power-down mode, the internal clock is stopped. The contents of the on-chip RAM and the SFRs are preserved. The port pins output the value held by their respective SFRs. OE is held HIGH, but CE is switched to HIGH, so the external ROM will not be enabled during power down, to save system power. 15.3 Wake-up from Power-down mode
Setting the PD flag in the PCON register forces the controller into the Power-down mode. Setting this flag enables the controller to be woken-up from the Power-down mode with either the external interrupts INT0 to INT8, or a reset operation. The wake-up operation has two basic approaches as explained in Section 15.3.1 and 15.3.2. 15.3.1 WAKE-UP USING INT0 TO INT8
Activation of any enabled interrupt will cause IDL (PCON.0) to be cleared by hardware thus terminating the Idle mode. The interrupt is serviced, and following the RETI instruction, the next instruction to be executed will be the one following the instruction that put the device in the Idle mode. The flag bits GF0 (PCON.2) and GF1 (PCON.3) may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When the Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits.
If any of the interrupts INT0 to INT8 is enabled, the device can be woken-up from the Power-down mode with these external interrupts. The user must ensure that the external clock is stable before the controller restarts, the internal clock will remain inactive for 18 clock periods. This is controlled by an on-chip delay counter. 15.3.2 WAKE-UP USING RST
To wake-up the SZF2002, the RST pin must be kept HIGH for a minimum of 12 clock cycles. The user must ensure that the external clock is stable before the controller restarts (at RST falling edge), the internal clock will remain inactive for 18 clock periods. This is controlled by an on-chip delay counter.
1998 Aug 26
27
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
15.4 Status of external pins
SZF2002
The status of the external pins during Idle and Power-down mode is shown in Table 20. Table 20 Status of external pins during Idle and Power-down modes MODE Idle Power-down MEMORY internal external internal external 15.5 CE 1 1 1 1 OE 1 1 1 1 PWM active active halted in last state halted in last state PORTS 1, 3 AND 4 port data port data port data port data DATA BUS Port 0 data floating Port 0 data floating
Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressed, the reset value of PCON is 00000000B. Table 21 Power Control Register (SFR address 87H) 7 SMOD 6 ARD 5 RFI 4 WLE 3 GF1 2 GF0 1 PD 0 IDL
Table 22 Description of PCON bits BIT 7 6 5 SYMBOL SMOD ARD RFI DESCRIPTION Double Baud rate. When set to a logic 1 the baud rate is doubled when the serial port SIO0 is being used in modes 1, 2 or 3 (except when Timer 2 is used). Setting this bit will force all MOVX instructions to access off-chip memory instead of AUX RAM. RFI reduction mode. Setting this bit will disable the ALE toggling during on-chip memory access. The SZF2002 does not have this signal during operational mode, but setting this bit will reduce the number of chip selects (CE) of the external memory (and thus power). Watchdog Load Enable. This flag must be set by software prior to loading the Watchdog Timer (T3). It is cleared when T3 is loaded. General purpose flag 1. General purpose flag 0. Power-down mode selection. Setting this bit activates the Power-down mode. If a logic 1 is written to both PD and IDL at the same time, PD takes precedence. Idle mode selection. Setting this bit activates the Idle mode.
4 3 2 1 0
WLE GF1 GF0 PD IDL
1998 Aug 26
28
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
16 I2C-BUS SERIAL I/O The serial port supports the twin line I2C-bus, which consists of a data line (SDA) and a clock line (SCL). These lines also function as the I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in 4 modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver.
SZF2002
These functions are controlled by the Serial Control Register (S1CON). S1STA is the Status Register whose contents may also be used as a vector to various service routines. S1DAT is the Data Shift Register and S1ADR is the Slave Address Register. Slave address recognition is performed by on-chip hardware. Figure 15 shows the block diagram of the I2C-bus serial I/O.
7 SLAVE ADDRESS S1ADR 7 SDA SHIFT REGISTER GC
0
0
ARBITRATION
SYNC LOGIC
SCL 7
BUS CLOCK GENERATOR 0 CONTROL REGISTER S1CON 7 STATUS REGISTER S1STA
MLB199
0
Fig.15 Block diagram of I2C-bus serial I/O.
1998 Aug 26
29
INTERNAL BUS
S1DAT
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
16.1 Serial Control Register (S1CON)
SZF2002
Table 23 Serial Control Register (SFR address D8H) 7 CR2 6 ENS1 5 STA 4 STO 3 SI 2 AA 1 CR1 0 CR0
Table 24 Description of S1CON bits BIT 6 SYMBOL ENS1 DESCRIPTION Enable serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to logic 1. START flag. When this bit is set in Slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START condition. STOP flag. With this bit set while in Master mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag. STO may also be set in Slave mode in order to recover from an error condition. In this case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases the SDA and SCL lines. The SIO then switches to the not addressed Slave receiver mode. The STOP flag is cleared by the hardware. SIO interrupt flag. This flag is set and an interrupt is generated, after any of the following events occur: * A START condition is generated in Master mode * Own slave address has been received during AA = 1 * The general call address has been received while GC (S1ADR.0) = 1 and AA = 1 * A data byte has been received or transmitted in Master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A STOP or START condition is received as selected slave receiver or transmitter. 2 AA Assert Acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is returned during the acknowledge clock pulse on the SCL line when: * Own slave address is received * General call address is received; GC (S1ADR.0) = 1 * A data byte is received while the device is programmed to be a Master receiver * A data byte is received while the device is a selected Slave receiver. When this bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own slave address or general call address is received. 7 1 0 CR2 CR1 CR0 Clock Rate selection. These 3 bits determine the serial clock frequency when SIO is in the Master mode. See Table 25.
5
STA
4
STO
3
SI
1998 Aug 26
30
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 25 Selection of the serial clock frequency (SCL) in a Master mode of operation CR2 0 0 0 0 1 1 1 1 16.2 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fclk DIVISOR 128 112 96 80 480 60 30 reserved
SZF2002
BIT RATE (kHz) AT fclk = 1 MHz 7.81 8.93 10.42 12.50 2.08 16.67 33.33 -
Serial Status Register (S1STA)
S1STA is a read-only register. The contents of this register may be used as a vector to a service routine. This optimizes the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface is given in Table 29. The register has only a valid vector to a service routine if the SI bit of the S1CON register is set, otherwise it is invalid, usually F8H. Table 26 Serial Status Register (SFR address D9H) 7 SC4 6 SC3 5 SC2 4 SC1 3 SC0 2 0 1 0 0 0
Table 27 Description of S1STA bits BIT 3 to 7 0 to 2 SYMBOL SC4 to SC0 - 5-bit status code; see Table 29. These three bits are always zero. DESCRIPTION
Table 28 Symbols used in Table 29 SYMBOL SLA R W ACK ACK DATA MST SLV TRX REC 7-bit slave address read bit write bit acknowledgement (acknowledge bit is logic 0) no acknowledgement (acknowledge bit is logic 1) data byte to or from I2C-bus master slave transmitter receiver DESCRIPTION
1998 Aug 26
31
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 29 Status codes S1STA VALUE MST/TRX mode 08H 10H 18H 20H 28H 30H 38H MST/REC mode 08H 10H 38H 40H 48H 50H 58H SLV/REC mode 60H 68H 70H 78H 80H 88H 90H 98H A0H SLV/TRX mode A8H B0H B8H C0H C8H Miscellaneous 00H F8H Own SLA and R have been received, ACK returned. Own SLA and W have been received, ACK returned. A START condition has been transmitted. A repeated START condition has been transmitted. Arbitration lost while returning ACK. SLA and R have been transmitted, ACK received. SLA and R have been transmitted, ACK received. DATA has been received, ACK returned. DATA has been received, ACK returned. A START condition has been transmitted. A repeated START condition has been transmitted. SLA and W have been transmitted, ACK has been received. SLA and W have been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. DATA of S1DAT has been transmitted, ACK received. Arbitration lost in SLA, R/W or DATA. DESCRIPTION
SZF2002
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned. General CALL has been received, ACK returned. Arbitration lost in SLA, R/W as MST. General CALL has been received. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with own SLA. DATA byte received, ACK returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. Previously addressed with general CALL. DATA byte has been received, ACK has been returned. A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX.
Arbitration lost in SLA and R/W as MST. Own SLA and R have been received, ACK returned. DATA byte has been transmitted, ACK received. DATA byte has been transmitted, ACK received. Last DATA byte has been transmitted (AA = 0), ACK received.
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition. No relevant state information available, SI = 0.
1998 Aug 26
32
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
16.3 Data Shift Register (S1DAT)
SZF2002
S1DAT contains the serial data to be transmitted or data which has just been received. The MSB (bit 7) is transmitted or received first; i.e. data shifted from right to left. The data received is only valid while the SI bit of the S1CON register is set. Table 30 Data Shift Register (SFR address DAH) 7 S1DAT.7 16.4 6 S1DAT.6 5 S1DAT.5 4 S1DAT.4 3 S1DAT.3 2 S1DAT.2 1 S1DAT.1 0 S1DAT.0
Address Register (S1ADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receiver/transmitter. Table 31 Address Register (SFR address DBH) 7 SLA6 6 SLA5 5 SLA4 4 SLA3 3 SLA2 2 SLA1 1 SLA0 0 GC
Table 32 Description of S1ADR bits BIT 7 to 1 0 SYMBOL SLA6 to SLA0 GC Own slave address. This bit is used to determine whether the general call address is recognized. When GC = 0, the general call address is not recognized; when GC = 1, the general call address is recognized. DESCRIPTION
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33
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
17 STANDARD SERIAL INTERFACE SIO0: UART This serial port is full duplex which means that it can transmit and receive simultaneously. It is also receive-buffered and can commence reception of a second byte before a previously received byte has been read from the register. (However, if the first byte has not been read by the time the reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed via the Special Function Register S0BUF. Writing to S0BUF loads the transmit register and reading S0BUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 16fclk. See Figs 17 and 18. Mode 1 10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). On receive, the stop bit goes into RB8 in the SFR S0CON. The baud rate is variable. See Figs 19 and 20. Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of a logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in S0CON, while the stop bit is ignored. The baud rate is programmable to either 116 or 132fclk. See Figs 21 and 22. Mode 3 11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. See Figs 23 and 24.
SZF2002
In all four modes, transmission is initiated by any instruction that uses S0BUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. 17.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th bit goes into RB8. The following bit is the stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated, but only if RB8 = 1. This feature is enabled by setting bit SM2 in S0CON. One use of this feature, in multiprocessor systems, is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is HIGH in an address byte and LOW in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be sent. The slaves that were not being addressed leave their SM2 bits set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
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34
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
17.2 Serial Port Control and Status Register (S0CON)
SZF2002
The Serial Port Control and Status Register is the Special Function Register S0CON. The register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Table 33 Serial Port Control Register (SFR address 98H) 7 SMO 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI
Table 34 Description of S0CON bits BIT 7 6 5 SYMBOL SM0 SM1 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In these modes, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be a logic 0. Enable serial reception. REN is set by software to enable reception, and cleared by software to disable reception. Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as desired. In Modes 2 and 3, is the 9th data bit received. In Mode 1, if SM2 = 0, then RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit time in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial transmission (except see SM2). Must be cleared by software. DESCRIPTION Mode select. These 2 bits are used to select the serial port mode; see Table 35.
4 3 2 1
REN TB8 RB8 TI
0
RI
Table 35 Selection of the serial port modes SMO 0 0 1 1 SM1 0 1 0 1 MODE Mode 0 Mode 1 Mode 2 Mode 3 DESCRIPTION shift register 8-bit UART 9-bit UART 9-bit UART BAUD RATE
1 1 f 16 clk 6fclk
variable or 132fclk variable
1998 Aug 26
35
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
17.3 Baud rates
SZF2002
Baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate as specified below: Timer 2 overflow rate Baud rate = ------------------------------------------------------16 Timer 2 can be configured for either `timer' or `counter' operation. In the most typical applications, it is configured for `timer' operation (C/T2 = 0). `Timer' operation is slightly different for Timer 2 when it is being used as a Baud Rate Generator. Normally, as a timer it would increment every machine cycle at a frequency of 16fclk. However, as a Baud Rate Generator it increments every state time at a frequency of fclk. In this case, the baud rate in Modes 1 and 3 is determined as shown by the following equation: f clk Baud rate = ----------------------------------------------------------------------------------------------------16 x { 65536 - ( RCAP2H; RCAP2L ) } Where (RCAP2H; RCAP2L) is the content of registers RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that the maximum baud rate depends on clock frequency and is determined by the following equation: f clk Maximum baud rate = --------------16 x 6 The Baud Rate Generator mode for Timer 2 is shown in Fig.16. This figure is only valid if RCLK0 = 1 or TCLK0 = 1 or RCLK1 = 1 or TCLK1 = 1. At roll-over TH2 does not set the TF2 bit in T2CON and therefore, will not generate an interrupt. Consequently, the Timer 2 interrupt does not need to be disabled when in the Baud Rate Generator mode. If EXEN2 is set, a HIGH-to-LOW transition on T2EX will set the EXF2 bit, also in T2CON, but will not cause a reload from (RCAP2H; RCAP2L) to (TH2 and TL2). Therefore, in this mode T2EX may be used as an additional external interrupt. When Timer 2 is operating as a timer (TR2 = 1), in the Baud Rate Generator mode, registers TH2 and TL2 should not be accessed (read or write). Under these conditions the timer increments every state time and therefore the results of a read or write may not be accurate. The registers RCAP2H and RCAP2L however, may be read but not written to. A write might overlap a reload and cause write and/or reload errors. If a write operation is required, Timer 2 or RCAP2H/RCAP2L should first be turned off by clearing the TR2 bit.
The baud rate in Mode 0 is fixed and may be calculated as: f clk Baud rate = -----6 The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON and may be calculated as: 2 Baud rate = ---------------- x f clk 32 * If SMOD = 0 (value on reset), the baud rate is 132fclk * If SMOD = 1, the baud rate is 116fclk. 17.3.1 USING TIMER 1 TO GENERATE BAUD RATES
SMOD
When Timer 1 is used as the Baud Rate Generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of the SMOD bit as follows: 2 Baud rate = ---------------- x Timer 1 overflow rate 32 The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either `timer' or `counter' operation in any of its 3 running modes. In typical applications, it is configured for `timer' operation, in the Auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by:
SMOD f clk 2 Baud rate = ---------------- x ---------------------------------------------------32 { 6 x ( 256 - TH1 ) } SMOD
By configuring Timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a 16-bit software reload, very low baud rates can be achieved. 17.3.2 USING TIMER 2 TO GENERATE BAUD RATES
Timer 2 is selected as a Baud Rate Generator by setting the RCLK0, TCLK0, RCLK1, or TCLK1 bit in T2CON. The Baud Rate Generator mode is similar to the Auto-reload mode, in that a roll-over in TH2 causes Timer 2 registers to be reloaded with the 16-bit value held in the registers RCAP2H and RCAP2L, which are preset by software.
1998 Aug 26
36
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
TIMER 1 overflow 2 0 fclk 1 SMOD TL2 (8 BITS) T2 PIN C/T2 = 1 control TR2 RELOAD TH2 (8 BITS) 1 0 RTCLK 16 UART receive/ transmit clock transition detector T2EX PIN control EXEN2 RCAP2L RCAP2H CLK
C/T2 = 0
EXF2
TIMER 2 interrupt (additional external interrupt)
MGM138
Fig.16 Timer 2 in Baud Rate Generator mode.
1998 Aug 26
37
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF RXD P3.0 ALT output function SHIFT
DS CL
Q
S0 BUFFER
ZERO DETECTOR
START S6 TX CLOCK
TX CONTROL
T1
SHIFT SEND
serial port interrupt SHIFT CLOCK R1
TXD P3.1 ALT output function
RX CLOCK REN RI START
RECEIVE
RX CONTROL
SHIFT 1 1 11111 0
INPUT SHIFT REGISTER SHIFT LOAD SBUF
RXD P3.0 ALT input function
S0 BUFFER
READ SBUF
INTERNAL BUS
MGC752
Fig.17 Serial port Mode 0.
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...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 s1...s6 ALE WRITE TO SBUF SEND SHIFT D0 D1 D2 D3 D4 D5 D6 D7 S6P2 T R A N S M I T RXD (DATA OUT)
Philips Semiconductors
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Fig.18 Serial port Mode 0 timing.
handbook, full pagewidth
39
TSC (SHIFT CLOCK) S3P1 T1 S6P1
WRITE TO SCON (CLEAR R1) R E C E I V E D0 S5P2 D1 D2 D3 D4 D5 D6 D7
RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK)
MLA567
Product specification
SZF2002
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
Timer 1 overflow
Timer 2 overflow DS Q CL S0 BUFFER TXD
2 0 SMOD 0 TCLK0 START 16 0 RCLK0 1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT TX CLOCK T1 1 SHIFT DATA SEND 1 ZERO DETECTOR SHIFT
TX CONTROL
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGM145
Fig.19 Serial port Mode 1.
1998 Aug 26
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TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD START BIT TI /16 RESET RX CLOCK START BIT R E C E I V E RXD D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT S1P1 T R A N S M I T
Philips Semiconductors
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Fig.20 Serial port Mode 1 timing.
handbook, full pagewidth
41
BIT DETECTOR SAMPLE TIME SHIFT RI
MLA569
Product specification
SZF2002
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
fclk
DS CL
Q
S0 BUFFER
TXD
2 0 SMOD at PCON.7 1 SHIFT ZERO DETECTOR
STOP BIT START 16 TX CLOCK
TX CONTROL
T1
SHIFT DATA SEND
serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGM144
Fig.21 Serial port Mode 2.
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TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD START BIT TI STOP BIT GEN /16 RESET RX CLOCK R E C E I V E START BIT RXD D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT S1P1 T R A N S M I T
Philips Semiconductors
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Fig.22 Serial port Mode 2 timing.
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43
BIT DETECTOR SAMPLE TIME SHIFT RI
MLA571
Product specification
SZF2002
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
INTERNAL BUS TB8 write to SBUF
Timer 1 overflow
Timer 2 overflow DS CL Q S0 BUFFER TXD
2 0 SMOD 0 TCLK0 START 16 0 RCLK0 1 serial port interrupt 16 sample HIGH-TO-LOW TRANSITION DETECTOR RX CLOCK START R1 LOAD SBUF SHIFT TX CLOCK T1 1 SHIFT DATA SEND 1 ZERO DETECTOR SHIFT
TX CONTROL
RX CONTROL
BIT DETECTOR RXD LOAD SBUF
INPUT SHIFT REGISTER (9-BITS) SHIFT
S0 BUFFER
READ SBUF
INTERNAL BUS
MGM143
Fig.23 Serial port Mode 3.
1998 Aug 26
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TX CLOCK WRITE TO SBUF DATA SEND S1P1 SHIFT TXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT T R A N S M I T
Philips Semiconductors
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Fig.24 Serial port Mode 3 timing.
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R E C E I V E
TI /16 RESET RX CLOCK START BIT RXD D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
BIT DETECTOR SAMPLE TIME SHIFT RI
MLA573
Product specification
SZF2002
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
18 INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU asynchronously to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution a multiple-source, two-priority-level, nested interrupt system is provided. The SZF2002 acknowledges interrupt requests from fifteen sources as follows: * INT0 to INT8 * Timer 0, Timer 1 and Timer 2 * I2C-bus serial I/O * UART * ADC. Each interrupt vectors to a separate location in program memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the Interrupt Enable Registers (IEN0 and IEN1). The priority level is selected via the Interrupt Priority Registers (IP0 and IP1). All enabled sources can be globally disabled or enabled. Figure 25 shows the interrupt system. 18.1 External interrupts INT2 to INT8
SZF2002
Port 1 interrupts are level sensitive. A Port 1 interrupt will be recognized when a level (longer than 2 machine cycles, HIGH or LOW, depending on the Interrupt Polarity Register) on P1.n is made. The interrupt request is not serviced until the next machine cycle. Figure 26 shows the external interrupt system. 18.2 Interrupt priority
Each interrupt source can be set to either a high priority or to a low priority. If interrupts of the same priority are requested simultaneously, the processor will branch to the interrupt polled first, according to Table 36. A low priority interrupt routine can only be interrupted by a high priority interrupt. A high priority interrupt routine can not be interrupted. Table 36 shows the interrupt vectors in order of priority. The vector indicates the ROM location where the appropriate interrupt service routine starts. Table 36 Interrupt vectors SYMBOL X0 (highest) S1 X5 T0 T2 X6 X1 X2 X7 T1 X3 X8 SO X4 ADC (lowest) VECTOR ADDRESS (HEX) 0003 002B 0053 000B 0033 005B 0013 003B 0063 001B 0043 006B 0023 004B 0073 SOURCE external interrupt 0 I2C-bus port external interrupt 5 Timer 0 Timer 2 external interrupt 6 external interrupt 1 external interrupt 2 external interrupt 7 Timer 1 external interrupt 3 external interrupt 8 UART external interrupt 4 ADC
Port 1 lines serve an alternative purpose as seven additional interrupts INT2 to INT8. When enabled, each of these lines (as well as INT0 and INT1) may wake-up the device from the Power-down mode. Using the Interrupt Polarity Register (IX1), each pin may be initialized to be either active HIGH or active LOW. IRQ1 is the Interrupt Request Flag Register. If the interrupt is enabled, each flag will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disabled. A low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt. A high priority interrupt routine can not be interrupted by any other interrupt. If two interrupt requests of different priority levels are received simultaneously, the request having the highest priority level will be serviced. If interrupt requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence (see Fig.25).
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46
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
INTERRUPT SOURCES X0
IEN0/1 REGISTERS
IP0/1
PRIORITY HIGH LOW
S1
X5
T0
T2
X1
X2
X7
T1
X3
X8
SO
X4
ADC GLOBAL ENABLE
MGD623
Fig.25 Interrupt system.
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47
INTERRUPT POLLING SEQUENCE
X6
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
IX1
IEN1/IEN0
IRQ1
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2 X1 GLOBAL ENABLE WAKE-UP X0
MGM139
Fig.26 External interrupt configuration.
18.3
Interrupt related registers
The registers IEN0, IEN1, IP0, IP1, IX1 and IRQ1 are used in conjunction with the interrupt system. Table 37 Special Function Registers related to the interrupt system ADDRESS A8H E8H B8H F8H E9H C0H REGISTER IEN0 IEN1 IP0 IP1 IX1 IRQ1 Interrupt Enable Register 0 Interrupt Enable Register 1 (INT2 to INT8) Interrupt Priority Register 0 Interrupt Priority Register 1 (INT2 to INT8 and ADC) Interrupt Polarity Register Interrupt Request Flag Register DESCRIPTION
1998 Aug 26
48
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
18.3.1 INTERRUPT ENABLE REGISTER 0 (IEN0)
SZF2002
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 38 Interrupt Enable Register 0 (SFR address A8H) 7 EA 6 ET2 5 ES1 4 ES0 3 ET1 2 EX1 1 ET0 0 EX0
Table 39 Description of IEN0 bits BIT 7 6 5 4 3 2 1 0 18.3.2 SYMBOL EA ET2 ES1 ES0 ET1 EX1 ET0 EX0 DESCRIPTION General enable/disable control. If EA = 0, no interrupt is enabled; if EA = 1, any individually enabled interrupt will be accepted. enable T2 interrupt enable I2C-bus interrupt enable UART SIO interrupt enable Timer 1 interrupt (T1) enable external interrupt 1 enable Timer 0 interrupt (T0) enable external interrupt 0
INTERRUPT ENABLE REGISTER 1 (IEN1)
Bit values: 0 = interrupt disabled; 1 = interrupt enabled. Table 40 Interrupt Enable Register 1 (SFR address E8H) 7 EAD 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
Table 41 Description of IEN1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL EAD EX8 EX7 EX6 EX5 EX4 EX3 EX2 enable external interrupt 8 enable external interrupt 7 enable external interrupt 6 enable external interrupt 5 enable external interrupt 4 enable external interrupt 3 enable external interrupt 2 DESCRIPTION enable ADC interrupt (external interrupt 9)
1998 Aug 26
49
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
18.3.3 INTERRUPT PRIORITY REGISTER 0 (IP0)
SZF2002
Bit values: 0 = low priority; 1 = high priority. Table 42 Interrupt Priority Register 0 (SFR address B8H) 7 - 6 PT2 5 PS1 4 PS0 3 PT1 2 PX1 1 PT0 0 PX0
Table 43 Description of IP0 bits BIT 7 6 5 4 3 2 1 0 18.3.4 SYMBOL - PT2 PS1 PS0 PT1 PX1 PT0 PX0 reserved Timer 2 interrupt priority level I2C-bus interrupt priority level UART SIO interrupt priority level Timer 1 interrupt priority level external interrupt 1 priority level Timer 0 interrupt priority level external interrupt 0 priority level DESCRIPTION
INTERRUPT PRIORITY REGISTER 1 (IP1)
Bit values: 0 = low priority; 1 = high priority. Table 44 Interrupt Priority Register 1 (SFR address F8H) 7 PADC 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Table 45 Description of IP1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL PADC PX8 PX7 PX6 PX5 PX4 PX3 PX2 ADC interrupt priority level external interrupt 8 priority level external interrupt 7 priority level external interrupt 6 priority level external interrupt 5 priority level external interrupt 4 priority level external interrupt 3 priority level external interrupt 2 priority level DESCRIPTION
1998 Aug 26
50
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
18.3.5 INTERRUPT POLARITY REGISTER (IX1)
SZF2002
Writing either a logic 1 or logic 0 to any Interrupt Polarity Register bit sets the polarity level of the corresponding external interrupt to an active HIGH or active LOW respectively. Table 46 Interrupt Polarity Register (SFR address E9H) 7 - 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Table 47 Description of IX1 bits BIT 7 6 5 4 3 2 1 0 18.3.6 SYMBOL - IL8 IL7 IL6 IL5 IL4 IL3 IL2 reserved external interrupt 8 polarity level external interrupt 7 polarity level external interrupt 6 polarity level external interrupt 5 polarity level external interrupt 4 polarity level external interrupt 3 polarity level external interrupt 2 polarity level DESCRIPTION
INTERRUPT REQUEST FLAG REGISTER (IRQ1)
Table 48 Interrupt Request Flag Register (SFR address C0H) 7 - 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2
Table 49 Description of IRQ1 bits BIT 7 6 5 4 3 2 1 0 SYMBOL - IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 reserved external interrupt 8 request flag external interrupt 7 request flag external interrupt 6 request flag external interrupt 5 request flag external interrupt 4 request flag external interrupt 3 request flag external interrupt 2 request flag DESCRIPTION
1998 Aug 26
51
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
19 CLOCK CIRCUITRY The SZF2002 is clocked with an external digital clock. The input must be driven with a digital square wave. Note that the duty cycle influences the timing to the external components, since both the positive and negative clock edges are used. 20 RESET To initialize the SZF2002 a reset is performed by either of two methods: * Applying an external signal to the RST pin * Watchdog Timer overflow. 20.1 External reset using the RST pin
SZF2002
The reset input for the SZF2002 is RST. A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (12 clock periods) while the clock is running. The CPU responds by executing an internal reset. Port pins adopt their reset state immediately after the RST goes HIGH. During reset, WE and OE, and CE are held HIGH. The external reset is asynchronous to the internal clock. The RST pin is sampled during state 5, phase 2 of every machine cycle. After a HIGH is detected at the RST pin, an internal reset is repeated until RST goes LOW. The reset circuitry is also affected by the Watchdog Timer as described in Section 12.5. The internal RAM is not affected by reset. When VDD is turned on, the RAM contents are indeterminate. 20.2 Power-on-reset
The device contains on-chip circuitry which switches the port pins to HIGH as soon as RST goes HIGH. The user must ensure that the RST pin is held HIGH until the external clock has stabilised. When RST goes LOW a further 3 cycles elapse before execution starts.
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52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
21 SPECIAL FUNCTION REGISTERS OVERVIEW ADDRESS (HEX) FF FE FC F8 F7 F0 E9 E8 E0 DB DA D9 D8 D0 CD CC CB CA C9 C8 C5 C4 C1 C0 B8 B0 A8 A0 T3 PWMP(1) PWM(1) IP1(1)(2) WDTKEY(1) B(2) IX1(1) IEN1(1)(2) ACC(2) S1ADR(1) S1DAT(1) S1STA(1) S1CON(1)(2) PSW(2) TH2(1) TL2(1) RCAP2H(1) RCAP2L(1) T2MOD(1) T2CON(1)(2) ADCH(1) ADCON(1) P4(1) IRQ1(1)(2) IP0(2) P3(2) IEN0(2) P2(2) NAME RESET VALUE (B) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 X000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XX00 X000 0000 0000 1111 1111 X000 0000 1111 1111 X000 0000 X000 0000 1111 1111 0000 0000 1111 1111 Watchdog Timer Prescaler Frequency Control Register Pulse Width Register Interrupt Priority Register 1 (INT2 to INT8 and ADC) Watchdog Timer enable B Register Interrupt Polarity Register 1 Interrupt Enable Register 1 Accumulator I2C-bus Slave Address Register I2C-bus Data Shift Register I2C-bus Serial Status Register I2C-bus Serial Control Register Program Status Word Timer 2 High byte Timer 2 Low byte Timer 2 Reload/Capture Register High byte Timer 2 Reload/Capture Register Low byte Timer/Counter 2 mode control Timer/Counter 2 Control Register ADC Result Register ADC Control Register Digital I/O Port Register 4 Interrupt Request Flag Register Interrupt Priority Register 0 Digital I/O Port Register 3 Interrupt Enable Register 0 Digital I/O Port Register 2 FUNCTION
SZF2002
1998 Aug 26
53
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
ADDRESS (HEX) 99 98 91 90 8D 8C 8B 8A 89 88 87 83 82 81 80 Notes 1. SZF2002 specific SFRs. 2. Bit addressed register. NAME S0BUF S0CON(2) ROMBANK(1) P1(2) TH1 TH0 TL1 TL0 TMOD TCON(2) PCON DPH DPL SP P0(2) RESET VALUE (B) XXXX XXXX 0000 0000 XXXX X000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 Serial Data Buffer Register 0 Serial Port Control Register 0 ROM bank Selection Register Digital I/O Port Register 1 Timer 1 High byte Timer 0 High byte Timer 1 Low byte Timer 0 Low byte Timer 0 and 1 Mode Control Register FUNCTION
SZF2002
Timer 0 and 1 Control/External Interrupt Control Register Power Control Register Data Pointer High byte Data Pointer Low byte Stack Pointer Digital I/O Port Register 0
1998 Aug 26
54
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
22 DEBUGGING SUPPORT For software development the SZF2002 is made compatible with the Nohau 80C51 In-Circuit Emulator (ICE). 22.1 Recommended equipment
SZF2002
The digital power VDD has to be connected to the pod. The ground of the pod must be connected to the ground of the target board via the black gnd-wire soldered to the pod Because the target supplies the pod the following power-up/power-down sequence is required: 1. Switch on target. 2. Switch on PC. 3. Switch off target. When using 3 V power from the target, note that the pod will drive the inputs up to 3.5 V. Some current will also flow through the VDD connection to the target. If the emulator is used together with an I2C-bus interface to a PC or together with an RS232-connection, use 3.3 V power for the target. This will reduce noise and disturbance on all input and output signals. In practice, it is seen that this will result in a more robust communication between the SZF2002 and Nohau. Both I2C-bus pins (SDA and SCL) need an external pull-up resistor. 22.4 Bank switching support
1. Nohau EMUL51-PC/EA768-BSW-42 42 MHz, 768-kbyte emulator memory board. 2. Nohau EMUL51-PC/ATR64-33, 33 MHz, 64-kbyte advanced trace memory board. 3. Nohau EMUL51-PC/POD-C32HF-42, external memory mode pod for a.o. 80C51/80C32. 22.2 Connecting the pod
The Nohau In-Circuit Emulator requires the following 80C51 pins: P0.0 to P0.7, P2.0 to P2.7, ALE, PSEN, RD, WR, EA and RST. When setting the SZF2002 in Debug mode (force DEBUG HIGH), these signals become available on the pins as described in Section 7.2 The connection between the SZF2002 and the emulator is shown in Fig.27. For emulation the Target board must be configured with the SZF2002 mounted, but without external Flash and RAM, or disabled by disconnecting the OE. On the Target board a 40-pin connector is required that has all the necessary 80C51 signals (Port 0, Port 2, PSEN, ALE, EA, RST, VDD and VSS). The 16 port pins are optional. The three banking bits are not standard 80C51 signals and are not available at the DIL40 80C51-connector of the pod. These three bits must be connected via three separate wires to the signals BS0 (LSB), BS1 and BS2 (MSB) on the pod. The emulator pod has a DIL40 socket for the 80C51 processor (on the upper side). By connecting the 40-pin connector to this socket the emulator will approach the SZF2002 as if it were a 80C51. The connector on the lower side of the pod is not used. The emulator acts as a memory emulator. 22.3 Powering the pod
If bank switching is required, the in-circuit emulator also needs the TRUE_A15 and the three banking bits A15 to A17. 16 port pins (selection of Ports 3 and 4) can also be connected to the emulator pod, however this is not necessary. When connected, the state of these ports can be traced. To set up the banking configuration the BM jumpers on the emulator board have to be set. The following set-up is recommended: 1. Jumper BM3 is out. 2. Jumper BM2 is out. 3. Jumper BM1is don't care. 4. Jumper BM0 is in. 22.5 Software recommendations The Keil/Franklin assembler and banked linker is well suited for use with the Nohau ICE (especially for banking configurations). The Nohau ICE communicates with the SZF2002 using MOVX instructions. Therefore, all MOVX instructions must be forced to access off-chip memory instead of internal AUX RAM by setting the ARD bit of the SFR PCON.
Because the SZF2002 is a 3 V circuit, the ICE pod must be powered by the target (supply from PC is not possible, see documentation for EMUL51-PC/POD-C32HF-42). Therefore, VDD and VSS for the SZF2002 are also required. The clock signal is not required on the pod.
1998 Aug 26
55
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
SZF2002 Flash
SZF2002 connector
adapter PCB
target PCB (Flash is disabled, doesn't need to be mounted)
socket for target processor
flat cable to PC
type 31A POD NOHAU emulator this socket not used
PC with emulator cards
MBK834
Fig.27 In-circuit emulation.
1998 Aug 26
56
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
23 INSTRUCTION SET
SZF2002
The SZF2002 uses a powerful instruction set which optimizes byte efficiency and execution speed. Assigned opcodes add new high-power operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz clock, 64 instructions execute in 0.5 s and 45 instructions execute in 1 s. Multiply and divide instructions execute in 2 s. For the description of the Data Addressing modes and Hexadecimal opcode cross-reference see Table 54. Table 50 Instruction set description: Arithmetic operations MNEMONIC Arithmetic operations ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A,Rr A,direct A,@Ri A,#data A Rr direct @Ri A Rr direct @Ri DPTR AB AB A add register to A add direct byte to A add indirect RAM to A add immediate data to A add register to A with carry flag add direct byte to A with carry flag add indirect RAM to A with carry flag add immediate data to A with carry flag subtract register from A with borrow subtract direct byte from A with borrow subtract indirect RAM from A with borrow subtract immediate data from A with borrow increment A increment register increment direct byte increment indirect RAM decrement A decrement register decrement direct byte decrement indirect RAM increment data pointer multiply A and B divide A by B decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 2* 25 26 and 27 24 3* 35 36 and 37 34 9* 95 96 and 97 94 04 0* 05 06 and 07 14 1* 15 16 and 17 A3 A4 84 D4 DESCRIPTION BYTES CYCLES OPCODE (HEX)
1998 Aug 26
57
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 51 Instruction set description: Logic operations MNEMONIC Logic operations ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A,Rr A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte exclusive-OR register to A exclusive-OR direct byte to A exclusive-OR indirect RAM to A exclusive-OR immediate data to A exclusive-OR A to direct byte exclusive-OR immediate data to direct byte clear A complement A rotate A left rotate A left through the carry flag rotate A right rotate A right through the carry flag swap nibbles within A 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 DESCRIPTION BYTES CYCLES
SZF2002
OPCODE (HEX)
5* 55 56 and 57 54 52 53 4* 45 46 and 47 44 42 43 6* 65 66 and 67 64 62 63 E4 F4 23 33 03 13 C4
1998 Aug 26
58
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 52 Instruction set description: Data transfer MNEMONIC Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD Note 1. MOV A,ACC is not permitted. A,Rr A,@Ri A,#data Rr,A Rr,direct Rr,#data direct,A direct,Rr direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data A,@A+DPTR A,@A+PC A,@Ri A,@DPTR @Ri,A @DPTR,A direct direct A,Rr A,direct A,@Ri A,@Ri move register to A move indirect RAM to A move immediate data to A move A to register move direct byte to register move immediate data to register move A to direct byte move register to direct byte move direct byte to direct move indirect RAM to direct byte move immediate data to direct byte move A to indirect RAM move direct byte to indirect RAM move immediate data to indirect RAM move code byte relative to DPTR to A move code byte relative to PC to A move external RAM (8-bit address) to A move external RAM (16-bit address) to A move A to external RAM (8-bit address) move A to external RAM (16-bit address) push direct byte onto stack pop direct byte from stack exchange register with A exchange direct byte with A exchange indirect RAM with A exchange LOW-order digit indirect RAM with A 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 DESCRIPTION BYTES CYCLES
SZF2002
OPCODE (HEX)
E* E5 E6 and E7 74 F* A* 7* F5 8* 85 86 and 87 75 F6 and F7 A6 and A7 76 and 77 90 93 83 E2 and E3 E0 F2 and F3 F0 C0 D0 C* C5 C6 and C7 D6 and D7
A,direct (note 1) move direct byte to A
DPTR,#data 16 load data pointer with a 16-bit constant
1998 Aug 26
59
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 53 Instruction set description: Boolean variable manipulation and Program and machine control MNEMONIC Boolean variable manipulation CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C clear carry flag clear direct bit set carry flag set direct bit complement carry flag complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag move direct bit to carry flag move carry flag to direct bit 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 1 2 DESCRIPTION BYTES
SZF2002
CYCLES
OPCODE (HEX)
C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 *1 12 22 32 1 02 80 73 60 70 40 50 20 30 10 B5 B4 B* B6 and B7 D* D5 00
Program and machine control ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ JC JNC JB JNB JBC CJNE CJNE CJNE CJNE DJNZ DJNZ NOP addr11 addr16 rel @A+DPTR rel rel rel rel bit,rel bit,rel bit,rel A,direct,rel A,#data,rel Rr,#data,rel Rr,rel direct,rel addr11 addr16 absolute subroutine call long subroutine call return from subroutine return from interrupt absolute jump long jump short jump (relative address) jump indirect relative to the DPTR jump if A is zero jump if A is not zero jump if carry flag is set jump if carry flag is not set jump if direct bit is set jump if direct bit is not set jump if direct bit is set and clear bit compare direct to A and jump if not equal compare immediate to A and jump if not equal compare immediate to register and jump if not equal decrement register and jump if not zero decrement direct and jump if not zero no operation 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
@Ri,#data,rel compare immediate to indirect and jump if not equal
1998 Aug 26
60
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 54 Description of the mnemonics in the Instruction set MNEMONIC Data addressing modes Rr direct @Ri #data #data 16 bit addr16 addr11 rel Working registers R0 to R7. 128 internal RAM locations and any special function register (SFR). DESCRIPTION
SZF2002
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank. 8-bit constant included in instruction. 16-bit constant included as bytes 2 and 3 of instruction. Direct addressed bit in internal RAM or SFR. 16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the 64 kbytes program memory address space. 111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes page of program memory as the first byte of the following instruction. Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to + 127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference * * 8, 9, A, B, C, D, E and F. 1, 3, 5, 7, 9, B, D and F. 0, 2, 4, 6, 8, A, C and E.
1998 Aug 26
61
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Aug 26 62 8 9 A B C D E F Note 1. MOV A, ACC is not a valid instruction. Philips Semiconductors Table 55 Instruction map
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
First hexadecimal character of opcode 0 1 2 3 4 5 6 7 0 NOP JBC bit,rel JB bit,rel JNB bit,rel JC rel JNC rel JZ rel JNZ rel SJMP rel MOV DTPR,#data16 ORL C,/bit ANL C,/bit PUSH direct POP direct MOVX A,@DTPR MOVX @DTPR,A 1 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 AJMP addr11 ACALL addr11 2 LJMP addr16 LCALL addr16 RET RETI ORL direct,A ANL direct,A XRL direct,A ORL C,bit ANL C,bit MOV bit,C MOV bit,C CPL bit CLR bit 3 RR A RRC A RL A RLC A ORL direct,#data ANL direct,#data XRL direct,#data JMP @A+DPTR MOVC A,@A+PC MOVC A,@A+DPTR INC DPTR CPL C CLR C
Second hexadecimal character of opcode 4 INC A DEC A ADD A,#data ADDC A,#data ORL A,#data ANL A,#data XRL A,#data MOV A,#data DIV AB SUBB A,#data MUL AB CJNE A,#data,rel SWAP A DA A CLR A CPL A 5 INC direct DEC direct ADD A,direct ADDC A,direct ORL A,direct ANL A,direct XRL A,direct MOV direct,#data MOV direct,direct SUBB A,direct 6 INC @Ri 0 DEC @Ri 0 1 ADD A,@Ri 0 1 ADDC A,@Ri 0 1 ORL A,@Ri 0 1 ANL A,@Ri 0 1 XRL A,@Ri 0 1 MOV @Ri,#data 0 1 MOV direct,@Ri 0 1 SUBB A,@Ri 0 1 MOV @Ri,direct 0 1 CJNE @Ri,#data,rel 0 1 XCH A,@Ri 0 1 XCHD A,@Ri 0 1 MOV A,@Ri 0 1 MOV @Ri,A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 7 8 9ABCDE INC Rr 123456 DEC Rr 123456 ADD A,Rr 123456 ADDC A,Rr 123456 ORL A,Rr 123456 ANL A,Rr 123456 XRL A,Rr 123456 MOV Rr,#data 123456 MOV direct,Rr 123456 SUB A,Rr 123456 MOV Rr,direct 123456 CJNE Rr,#data,rel 123456 XCH A,Rr 123456 DJNZ Rr,rel 123456 MOV A,Rr 123456 MOV Rr,A 123456 F 7 7 7 7 7 7 7 7 7 7 7 7 7 7
CJNE A,direct,rel XCH A,direct DJNZ direct,rel MOV A,direct(1) MOV direct,A
SETB SETB bit C MOVX A,@Ri 0 1 MOVX @Ri,A 0 1
Product specification
7 7
SZF2002
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
24 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI II and IO Ptot Tstg Tamb Tj supply voltage input voltage on any pin with respect to ground (VSS) DC current on any input or output total power dissipation storage temperature operating ambient temperature operating junction temperature PARAMETER MIN. -0.5 -0.5 - - -65 -40 -40 +5 MAX.
SZF2002
UNIT V V mA mW C C C
VDD + 0.5 tbf 500 +150 +85 +125
25 DC CHARACTERISTICS VDD = 2.7 to 3.3 V; VSS = 0 V; Tamb = -40 to +85 C; see note 1; all voltages are with respect to VSS; unless otherwise specified. SYMBOL Supply VDD IDD operating supply voltage operating supply current VDD = 3.0 V; fCLK = 8 MHz; note 2 VDD = 3.0 V; fCLK = 3.58 MHz; note 2 IDD(idle) Idle mode supply current VDD = 3.0 V; fCLK = 8 MHz; note 3 VDD = 3.0 V; fCLK = 3.58 MHz; note 3 IDD(pd) VIL VIH ILI IIL Outputs VOL VOH IOL IOH RRST VDDA IDDA LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current RST pull-down resistor - 4.0 -4.0 120 - - - 160 0.4 - - - 250 V V mA mA k VDD - 0.4 - Power-down mode current VDD = 3.0 V; Tamb = 25 C; note 4 Inputs (note 5) LOW-level input voltage HIGH-level input voltage input leakage current input pull-up current VSS < Vi < VDD; VDD = 3.0 V; Tamb = 25 C Input = HIGH VSS 0.8VDD -1 - - - - - 0.2VDD VDD +1 tbf V V A A 2.7 - - - - - - - - - - - 3.3 9 2.5 5.0 1.5 10 V mA mA mA mA A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog inputs analog supply voltage supply current operating VDDA = 3.0 V; fCLK = 8 MHz; note 2 VDD - 0.5 - - - VDD + 0.5 V 0.5 mA
Notes to the DC characteristics 1. Loading ports and busses may cause spurious noise pulses to be superimposed on the output voltage. 1998 Aug 26 63
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
2. The operating supply current is measured with all output pins disconnected; CLK driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; EA = RST = Port 0 = VDD. 3. The Idle mode supply current is measured with all output pins disconnected; CLK driven with tr = tf = 10 ns; VIL = VSS; VIH = VDD; EA = Port 0 = VDD. 4. The power-down current is measured with all output pins disconnected; CLK connected to VSS; EA = Port 0 = VDD; RST = VSS. 5. The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I2C-bus specification. Therefore, an input voltage below 0.3VDD will be recognized as a logic 0 and an input voltage above 0.7VDD will be recognized as a logic 1. 26 ADC CHARACTERISTICS SYMBOL VIN(ADC) VDDA IDDA CAIN RAIN Ge OSe DNL INL Mctc VI(slope) Notes 1. All ADC inputs require an external divide-by-2 voltage divider. 2. Gain error: the maximum difference between actual and ideal slope. 3. Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code transition. 4. Differential non-linearity: the difference between the actual and ideal code widths. 5. Integral non-linearity: maximum deviation from straight line. 6. Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on sampling basis. PARAMETER ADC input voltage analog supply voltage supply current operating analog on-chip input capacitance analog on-chip input impedance Gain error; note 2 zero-offset error; note 3 differential non-linearity; note 4 Integral non-linearity; note 5 channel-to-channel matching; note 6 input voltage slope fclk = 8 MHz VDDA = 3.0 V; fclk = 8 MHz note 1 CONDITIONS MIN. VSSA VDD - 0.5 - - 10 -1 -1 -0.5 -1 - -0.15 TYP. - - - - - - - - - - - MAX. 0.5VDDA VDD + 0.5 0.5 2 - +1 +1 +0.5 +1 1
2
UNIT V V mA pF M % LSB LSB LSB LSB V/ms
+0.15
1998 Aug 26
64
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
(1)
(2)
255 254 253 252 251 250
code out
(5) (4)
5 4 3 2 1 0 1 2 3 1 LSB (ideal) 4 5 6 7 250 251 252 253 254 255 VIN(A)(LSBideal) 1LSB = VDDA - VSSA 255
MGM135
(3)
zero offset error
(1) (2) (3) (4)
The ideal transfer curve. The actual transfer curve. Differential non-linearity (DNL). Integral non-linearity (INL). (5) Gain error (Ge).
Fig.28 Analog-to-Digital conversion characteristics.
1998 Aug 26
65
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
27 AC CHARACTERISTICS Table 56 Timing with respect to CE, OE and WE SYMBOL General (see Fig.29) tXCLKH tXCLKL Tcy(XCLK) t(CEL-OEL)1 t(OEL)1 t(CEH-OEH)1 t(CEL)1 t(CEL-WEL)1 t(WEL)1 t(CEH-WEH)1 tsu(OE-D)2 tsu(CEL-D)2 tsu(D-WEL)3 t(CEL-DV)3 tsu(D-SM)2 th(SM-D)2 th(WEH-D)3 th(CEH-D)3 tsu(A-CEL)1 th(CEH-A)1 t(CEL-OEL)4 t(OEL)4 t(CEH-OEH)4 XCLK HIGH time XCLK LOW time XCLK cycle time 31.25 31.25 62.5 - - 0 - - - 0 - - - - - 0 - - - - - - 0 - - - - - - - - - - - - - - - - - - - - - - - - - -
1 7
SZF2002
PARAMETER
MIN.
TYP
MAX.
UNIT
ns ns ns
Memory Access (Figs 29 and 30) CE LOW to OE LOW (data cycle) OE LOW time (data cycle) CE HIGH to OE HIGH (data cycle) CE LOW time (data cycle) CE LOW to WE LOW (data cycle) WE LOW time (data cycle) CE HIGH to WE HIGH (data cycle) Data set-up time from OE (data read cycle) Data set-up time from CE LOW (data read cycle) Data set-up time to WE LOW (data write cycle) Data valid time from CE LOW (data write cycle) Data set-up time to sample moment (data read cycle); note 1 Data hold time from sample moment (data read cycle); note 1 Data hold time from WE HIGH (data write cycle) Data hold time from CE HIGH (data write cycle) Address set-up time to CE LOW (data cycle) Address hold time from CE HIGH (data cycle) CE LOW to OE LOW (code fetch cycle) OE LOW time (code fetch cycle) CE HIGH to OE HIGH (code fetch cycle)
2tCLK 2tCLK
+3 +7
ns ns ns ns
12 4tCLK
1 7 2tCLK 2tCLK
+5 +8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
13 3tCLK - 18
7 1 2tCLK 2tCLK
- 18 ns -3
3 8 - tCLK - 20 tCLK - 10 1 t 2 CLK - 5 tCLK
1 3 2tCLK 2tCLK
2
1998 Aug 26
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SYMBOL t(CEL)4 tsu(OE-D)4 tsu(CEL-D)4 tsu(D-SM)4 th(SM-D)4 tsu(DZ-OEL) th(DZ-OEH) tsu(A-CEL)4 th(CEH-A)4 Notes PARAMETER CE LOW time (code fetch cycle) Data set-up time from OE (code fetch cycle) Data set-up time from CE LOW (code fetch cycle) Data hold time from sample moment (code fetch cycle) Data bus high-impedance set-up time to OE LOW (data read cycle); (Code Fetch cycle) Data bus high-impedance hold time from OE HIGH (data read cycle); (code fetch cycle) Address set-up time to CE LOW (code fetch cycle) Address hold time from CE HIGH (code fetch cycle) - - - 0
1 t 2 CLK 1 t 2 CLK
SZF2002
MIN.
TYP - - - - -
3
MAX. 2tCLK
2tCLK
UNIT ns
- 18 ns ns ns ns ns ns
2tCLK - 18 8 - - -
1 1 2tCLK 2tCLK
Data set-up time to sample moment (code fetch cycle), note 2 - + 12
- - - -
- 2; tCLK - 11
- -
-4
ns ns
1. Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken into account also. This results in 3tCLK - 10 ns from OE LOW (or 72tCLK - 10 ns from CE LOW) maximum. 2. Sample moment for code fetch cycles is on negative clock edge in state S2 or S4, the internal clock skew must be taken into account also. This results in 32tCLK - 10 ns from OE LOW (or 2tCLK - 10 ns from CE LOW) maximum.
1998 Aug 26
67
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
S1 to S6: one machine cycle S4 XCLK tXCLKH tXCLKL TCY(XCLK)
(2)
SZF2002
handbook, full pagewidth
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
A2/ALE(1)
A3/PSEN(1)
A0/RD(1)
A1/WR(1) t(CEL-OEL)1 t(CEH-OEH)1 t(OEL)1 t(CEL-OEL)4 t(CEH-OEH)4
OE t(CEL)1 CE t(CEH-WEH)1 t(CEL-WEL)1 WE tsu(DZ-OEL) tsu(OE-D)2 tsu(CEL-D)2 tsu(D-SM)2 D0 to D7 code in data out tsu(D-WEL)3 t(CEL-DV)3 tsu(A-CEL)1 A0 to A17 data in th(SM-D)2
(3)
t(WEL)1
th(DZ-OEH)
tsu(CEL-D)4 tsu(OE-D)4 tsu(D-SM)4 code in th(SM-D)4 Code sample moment tsu(A-CEL)4
(3)
th(WEH-D)3
code in
Data sample moment th(CEH-A)1
th(CEH-A)4
CODE FETCH
WRITE(
)/READ(
)
CODE FETCH
CODE FETCH
MGM354
(1) A0 to A3 alternative functions (PSEN, ALE, WR and RD) show Debug mode timing; data bus carries low address on falling ALE edge. (2) Skipped ALE pulse because of MOVX instruction. (3) (Last) data sample moment.
Fig.29 External program memory access, w.r.t. CE, OE, and WE.
1998 Aug 26
68
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
Table 57 Timing figures with respect to RAMCE, OE and WEL SYMBOL General (see Fig.29) tXCLKH tXCLKL Tcy(XCLK) t(RCEL-OEL) t(OEL) t(RCEH-OEH) t(RCEL) t(RCEL-WEL) t(WEL) t(RCEH-WEH) tsu(OEL-D) tsu(RCEL-D) tsu(D-WEL) t(RCEL-DV) tsu(D-SM) th(SM-D) th(WEH-D) th(RCEH-D) tsu(A-RCEL) th(RCEH-A) tsu(DZ-OEL) th(OEH-DZ) Notes XCLK HIGH time XCLK LOW time XCLK cycle time 31.25 31.25 62.5 - - 0 - - - 0 - - - - - 0 - - - -
1 1 2tCLK + 1 2tCLK
SZF2002
PARAMETER
MIN.
TYP. - - - - - - - - - - - - - - - - - - - - - - - - -
1 7
MAX.
UNIT
ns ns ns -3
Memory Access (Figs 29 and 30) RAMCE LOW to OE LOW OE LOW time RAMCE HIGH to OE HIGH RAMCE LOW time RAMCE LOW to WE LOW WE LOW time RAMCE HIGH to WE HIGH Data set-up time from OE LOW Data set-up time from RAMCE LOW Data set-up time to WE LOW Data valid time from RAMCE LOW Data set-up time to sample moment, note 1 Data hold time from sample moment; note 1 Data hold time from WE HIGH Data hold time from RAMCE HIGH Address set-up time to RAMCE LOW Address hold time from RAMCE HIGH Data bus high-impedance set-up time to OE LOW Data bus high-impedance hold time from OE HIGH
2tCLK
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2tCLK + 8
6 4tCLK - 1
1 7 2tCLK
-2
2tCLK + 7
7 3tCLK - 18
7 1 2tCLK - 20 2tCLK
+3
4 8 - tCLK - 7 tCLK - 14
1 2tCLK
tCLK - 7 - -
- 10
1. Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken into account also. This results in 3tCLK - 10 ns from OE LOW (or 72tCLK - 10 ns from RAMCE LOW) maximum.
1998 Aug 26
69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
SZF2002
handbook, full pagewidth
S1 to S6: one machine cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
XCLK tXCLKH tXCLKL
(2)
A2/ALE(1)
A3/PSEN(1)
A0/RD(1)
A1/WR(1) t(RCEL-OEL) OE t(CEL) RAMCE t(RCEH-WEH) t(RCEL-WEL) WE tsu(RCEL-D) tsu(OEL-D) tsu(DZ-OEL) D0 to D7 code in tsu(D-SM) data out tsu(D-WEL) t(RCEL-DV) tsu(A-RCEL) A0 to A17 data in th(SM-D) Code sample moment(3) th(RCEH-A) code in code in th(OEH-DZ) th(WEH-D) t(WEL) t(OEL) t(RCEH-OEH)
Data sample moment(3)
CODE FETCH(4)
WRITE(
)/READ(
)
CODE FETCH(4)
CODE FETCH(4)
MGM355
(1) (2) (3) (4)
A0 to A3 alternative functions (PSEN, ALE, WR and RD) show Debug mode timing (Data bus carries low address on falling ALE edge. Skipped ALE pulse because of MOVX instruction. (Last) data sample moment. Code fetch only if CE is active (not shown). CE and RAMCE are never active at the same time.
Fig.30 External RAM access w.r.t. RAMCE, OE and WE.
1998 Aug 26
70
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
28 PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SZF2002
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X Lp A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
14.15 14.15 13.85 13.85
ISSUE DATE 95-12-19 97-07-15
1998 Aug 26
71
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
29 SOLDERING 29.1 Introduction
SZF2002
If wave soldering cannot be avoided, for LQFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 29.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 29.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 29.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all LQFP packages with a pitch (e) equal or less than 0.5 mm.
1998 Aug 26
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
30 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SZF2002
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 31 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 32 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Aug 26
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Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
NOTES
SZF2002
1998 Aug 26
74
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
NOTES
SZF2002
1998 Aug 26
75
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
455104/100/01/pp76
Date of release: 1998 Aug 26
Document order number:
9397 750 02944

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